Copper Lay Out

COPPER LAY OUT - Conductive Layers

1. “Flashes” for pads are required when generating output; it is kindly suggested to use not “painted” pads (i.e. pads filled with small draws) nor for big copper area or copper planes: in these cases it is suggested to realized a contourized area or a polygon area which are usable features in gerber RS-274X outputs.

2. The board outline must be also present in the copper layers: to do this, it is usable a small line, typical is a 0.50mm (20mil) wide, where the center of the line is the exact board outline. This line will be removed during the artwork film generation for the production.

3. All copper pads must be removed from NPTH hole’s positions if those pads are not used or connected to any track or copper area. If any copper pads is needed on NPTH hole’s position, it is required to use a minimum anular ring as already recommended.
Important features (for multilayers pcb): if holes are not connected on a particular inner layer, do not put at that position any pad in the inner layers drawing. If present all unconnected pads on the inner layers will be removed in any case.

4. Small areas of unconnected copper or narrow copper webs and slivers which can lead to problems in production, must be not used if not absolutely needed. Any way those area must meet classification criterion for minimum track width and gap. Typical situation are: A= respect minimum line. – B= Avoid if possible. – C= Preferred design

5. Thermal pads ( PTH ) should be properly defined considering the pattern classification of annular rings, track widths (thermal segment) and gaps. Usually they are realized with a gap and a line width of 0.20mm (8mil).

6. Copper plane or copper fulfilled areas should be realized with full copper lay out rather than grid patterns. If grid patterns is preferred, the following minimum settings must be applied:

- Minimum tracks width of grid = 0.125mm (5mil)
- Minimum track to track gap ( no copper area) = 0.125mm (5mil)

Important note: any copper grid that does not meet these minimum requirements could be converted into a full copper plane.

7. Due to the alignment tolerances between drawing and mechanical processes during production, a minimal clearance between edge of board and pattern is needed; depending on applied processes this gap is:

- routed boards:
- 0.20mm (8mil) on outer layers
- 0.40mm (16mil) on inner layers

- scoring boards (V-cut):
- 0.40mm (16mil) on outer and inner layers (if pcb thickness is >1.2mm)
- 0.30mm (12mil) on outer and inner layers (if pcb thickness is <= 1.2mm)

Note: if the pcb has copper pads or a copper area or a copper plane to extend up to the board edge ( so to reduce the exposed values for the copper to pcb edge gap), this must be clearly indicated in the mechanical layer. This should only be used where absolutely necessary because the copper could be ripped or relieved or peeled away by the mechanical tool.

8. Only PcbOnDemand service allowed to do the copper plating of the board edge (or part of it): this must be clearly indicated in the mechanical layer.

9. Any text placed in a copper or other layers has to comply with the design rules (depending on different class).

Note: all text must be correctly readable, so considering that a pcb is always viewed during CAM/CAD operations from top to bottom side trough them, the text on the top layers (copper or resist mask or legend) of your board must be readable and text on the bottom layers un-readable (mirrored).

10. “Peelables” occur during production when thin/small/short/narrow pieces of photo resist material enclosed by pads, traces and/or planes peel away during processing, causing short or open circuits in the pcb. For this all drawings ( particularly copper lines/pads even within the same electrical net), must comply with the design rules ( minimum line and minimum gap).

11. For gold connectors (fingers) do not place any plated holes (PTH), SMD or other pads closer than 2.00mm (80mil) to the gold fingers.

12. The proper layer sequence for a multilayer board must be provided: typical system is to indicate it naming the files in clear way ( top, 2, 3,…., bot layers is clear enough). To get readability of the different layers on the pcb, the layers numbers must be positioned in the copper drawing in such a way that they do not overlap ( so they can be seen through the complete material at the end of production process): in this case it is suggested to use 1 to indicate top layer and last number to indicate bottom layer.

13. A Build Up specification must be included in the gerber mechanical layer: this document indicate required thickness of all layers, including copper, soldermask, legend and finishing; also other additional layers like peelable material or carbon ink must be indicated in the same document. It also indicates the correct sequence as corresponding data file name.

Note: include a simple ASCII text file with the data indicating which file is to be used for which layer, preferably already in the correct build-up sequence (this is the least preferred solution: it is better if the build-up is indicated in the Gerber data as in the previous 3 suggestions).

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